In-Memory Computing by Using Nano-ionic Memristive Devices

By reaching to the CMOS scaling limitation based on the Moore’s law and due to the increasing disparity between the processing units and memory performance, the quest is continued to find a suitable alternative to replace the conventional technology. The recently discovered two terminal element, memristor, is believed to be one of the most promising candidates for future very large scale integrated systems. This thesis is comprised of two main parts, (Part I) modeling the memristor devices, and (Part II) memristive computing. The first part is presented in one chapter and the second part of the thesis contains five chapters. The basics and fundamentals regarding the memristor functionality and memristive computing are presented in the introduction chapter. A brief detail of these two main parts is as follows: Part I: Modeling- This part presents an accurate model based on the charge transport mechanisms for nanoionic memristor devices. The main current mechanism in metal/insulator/metal (MIM) structures are assessed, a physic-based model is proposed and a SPICE model is presented and tested for four different fabricated devices. An accuracy comparison is done for various models for Ag/TiO2/ITO fabricated device. Also, the functionality of the model is tested for various input signals. Part II: Memristive computing- Memristive computing is about utilizing memristor to perform computational tasks. This part of the thesis is divided into neuromorphic, analog and digital computing schemes with memristor devices. – Neuromorphic computing- Two chapters of this thesis are about biologicalinspired memristive neural networks using STDP-based learning mechanism. The memristive implementation of two well-known spiking neuron models, Hudgkin-Huxley and Morris-Lecar, are assessed and utilized in the proposed memristive network. The synaptic connections are also memristor devices in this design. Unsupervised pattern classification tasks are done to ensure the right functionality of the system. – Analog computing- Memristor has analog memory property as it can be programmed to different memristance values. A novel memristive analog adder is designed by Continuous Valued Number System (CVNS) scheme and its circuit is comprised of addition and modulo blocks. The proposed analog adder design is explained and its functionality is tested for various numbers. It is shown that the CVNS scheme is compatible with memristive design and the environment resolution can be adjusted by the memristance ratio of the memristor devices. – Digital computing- Two chapters are dedicated for digital computing. In the first one, a development over IMPLY-based logic with memristor is provided to implement a 4:2 compressor circuit. In the second chapter, A novel resistive over a novel mirrored memristive crossbar platform. Different logic gates are designed with the proposed memristive logic method and the simulations are provided with Cadence to prove the functionality of the logic. The logic implementation over a mirrored memristive crossbars is also assessed

A Review of Graphene-Based Memristive Neuromorphic Devices and Circuits

As data processing volume increases, the limitations of traditional computers and the need for more efficient computing methods become evident. Neuromorphic computing mimics the brain's low-power and high-speed computations, making it crucial in the era of big data and artificial intelligence. One significant development in this field is the memristor, a device that exhibits neuromorphic tendencies. The performance of memristive devices and circuits relies on the materials used, with graphene being a promising candidate due to its unique properties. Researchers are investigating graphene-based memristors for large-scale, sustainable fabrication. Herein, progress in the development of graphene-based memristive neuromorphic devices and circuits is highlighted. Graphene and its common fabrication methods are discussed. The fabrication and production of graphene-based memristive devices are reviewed and comparisons are provided among graphene- and nongraphene-based memristive devices. Next, a detailed synthesis of the devices utilizing graphene-based memristors is provided to implement the basic building blocks of neuromorphic architectures, that is, synapses, and neurons. This is followed by reviewing studies building graphene memristive spiking neural networks (SNNs). Finally, insights on the prospects of graphene-based neuromorphic memristive systems including their device- and network-level challenges and opportunities are given

Simulation of memristive crossbar arrays for seizure detection and prediction using parallel Convolutional Neural Networks [Formula presented]

For epileptic seizure detection and prediction, to address the computational bottleneck of the von Neumann architecture, we develop an in-memory memristive crossbar-based accelerator simulator. The simulator software is composed of a Python-based neural network training component and a MATLAB-based memristive crossbar array component. The software provides a baseline network for developing deep learning-based signal processing tasks, as well as a platform to investigate the impact of weight mapping schemes and device and peripheral circuitry non-idealities

Optimized Implementation of Memristor-Based Full Adder by Material Implication Logic

Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.Comment: International Conference on Electronics Circuits and Systems (ICECS), 201

Development of Compute-in-Memory Memristive Crossbar Architecture with Composite Memory Cells

In this chapter, we discuss the compute-in-memory memristive architectures and develop a 2M1M crossbar array which can be applied for both memory and logic applications. In the first section of this chapter, we briefly discuss compute-in-memory memristive architectural concepts and specifically investigate the current state off the art composite memristor-based switch cells. Also, we define their applications e.g. digital/analog logic, memory, etc. along with their drawbacks and implementation limitations. These composite cells can be designed to be adapted into different design needs can enhance the performance of the memristor crossbar array while preserving their advantages in terms of area and/or energy efficiency. In the second section of the chapter, we discuss a 2M1M memristor switch and its functionality which can be applied into memory crossbars and enables both memory and logic functions. In the next section of the chapter, we define logic implementation by using 2M1M cells and describe variety of in-memory digital logic 2M1M gates. In the next section of the chapter, 2M1M crossbar array performance to be utilized as memory platform is described and we conceived pure memristive 2M1M crossbar array maintains high density, energy efficiency and low read and write time in comparison with other state of art memory architectures. This chapter concluded that utilizing a composite memory cell based on non-volatile memristor devices allow a more efficient combination of processing and storage architectures (compute-in-memory) to overcome the memory wall problem and enhance the computational efficiency for beyond Von-Neumann computing platforms

Mitigating State-Drift in Memristor Crossbar Arrays for Vector Matrix Multiplication

In this Chapter, we review the recent progress on resistance drift mitigation techniques for resistive switching memory devices (specifically memristors) and its impact on the accuracy in deep neural network applications. In the first section of the chapter, we investigate the importance of soft errors and their detrimental impact on memristor-based vector–matrix multiplication (VMM) platforms performance specially the memristance state-drift induced by long-term recurring inference operations with sub-threshold stress voltage. Also, we briefly review some currently developed state-drift mitigation methods. In the next section of the chapter, we will discuss an adaptive inference technique with low hardware overhead to mitigate the memristance drift in memristive VMM platform by using optimization techniques to adjust the inference voltage characteristic associated with different network layers. Also, we present simulation results and performance improvements achieved by applying the proposed inference technique by considering non-idealities for various deep network applications on memristor crossbar arrays. This chapter suggests that a simple low overhead inference technique can revive the functionality, enhance the performance of memristor-based VMM arrays and significantly increases their lifetime which can be a very important factor toward making this technology as a main stream player in future in-memory computing platforms

CMOS and memristive hardware for neuromorphic computing

The ever-increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes inspiration from the highly parallel, low power, high speed, and noise-tolerant computing capabilities of the brain, may provide such a shift. To that end, various aspects of the brain, from its basic building blocks, such as neurons and synapses, to its massively parallel in-memory computing networks have been being studied by the huge neuroscience community. Concurrently, many researchers from across academia and industry have been studying materials, devices, circuits, and systems, to implement some of the functions of networks of neurons and synapses to develop bio-inspired (neuromorphic) computing platforms

In-Memory Memristive Transformation Stage of Gaussian Random Number Generator

In this work, we present a modification to the digital Wallace-based Gaussian Random Number Generator (GRNG) by implementing an in-memory memristive dot-product engine in place of the vector-matrix multiplication (VMM) stage. The dot-product engine provides an analog interface to the GRNG with statistical robustness and better resource efficiency. One modification with three different structures is proposed and evaluated by the statistical test pass rates and benchmarked against the digital implementations. The best-proposed modification achieved a 95.8% test pass rate for 100 iterative small pool generation while requiring 23.6% and 44.4% less power and area consumption